1. Field of the Invention
The present invention relates generally to computer bus assemblies and interconnects and more particularly to an extensible bus assembly with L-shaped interconnection devices.
2. Description of the Prior Art
Interconnections between a microcomputer bus system and the various electronic devices within a computer are typically fashioned via a plurality of signal line stub lengths. A common bus structure is the synchronous backplane interconnect (SBI). The term "bus" herein means a conductor used for transmitting data and/or power signals. The SBI is basically a straight transmission line located along the rear of the computer casing. Since the SBI is a straight line, stub length interconnections from the various devices will vary greatly (i.e., devices within the computer cannot all be positioned immediately adjacent to the bus). For example, the communication path between the central processing unit (CPU) and a memory unit will have two differing stub length interconnects where the first stub length from the CPU to the bus might be longer than the second stub length from the bus to memory.
One problem with this bus interconnect arrangement is signal reflection which occurs due to the different stub lengths attached at various locations along the straight bus. Each stub length will have a characteristic reflection problem dependent on the geometries of the stub length, as well as the frequency of the signal and the edge rate (i.e., the slope of a signal which travels along the stub). In the example above, one would expect to encounter greater signal reflection on the interconnect between the CPU and the bus, than the interconnect between the bus and memory.
In addition to the reflection problem, varying stub lengths create varying impedances. As with the signal reflection problem, characteristic impedance based on the stub length further impedes signal strength and fidelity thereby increasing overall signal distortion. Varying impedances are also encountered along loaded and unloaded portions of the SBI. Portions of the SBI which support a load (i.e., some circuitry) will have a different characteristic impedance than a portion of the SBI which is unloaded.
Further, prior art bussed system interconnect geometries such as the SBI have a restricted profile. The prior art bus profiles have a lower limit based on the length of the bus structure and the number of devices connected to the bus. In other words, the bus profile can only be so small, given that the bus, which comprises one straight transmission line along the rear of the computer casing, must accommodate a number of input/output (I/O) printed circuit boards which are plugged into the bus. The only way to reduce the bus' profile is to reduce the number of I/O boards, or cards, which are plugged into the bus; this cannot be done below a certain necessary minimum number of I/O cards.
Another problem of prior art computer bus structures is the limited number of cards which can be plugged into the bus. Microcomputer bus systems generally contain a set number of used and unused slots. Once the unused slots are fully occupied, the only method of adding additional devices is to add a bus extender. The bus extender device adds to the cost of the bus system and introduces an additional source for signal distortion. Further, bus extenders typically result in performance degradation which must be accommodated by introducing wait states into the data transmission schemes.
It would be advantageous if a bus system interconnect could have uniform stub lengths such that the signal distortion problems associated with reflection and impedance would be substantially lessened. A bus system without unloaded portions would further decrease signal impedance.
Further advantages would be realized if the interconnects provided a lower profile than conventional bussed system interconnects, and if the bus system was inherently extensible which would obviate the need for wait states.